$ Hello world, 284x!{uni}[WEI] svn:4809cf907639f112 (Dec 22 2017 11:05:11) flash_type = 2, secure_type = 2 b8062204=0 [go kb]KRRRROOOONNRNRNRUU"U#U$ U-Boot 2012.07-sw_2831/trunk/2831_Hikeen_1222/bootcode-svn7617 (Aug 03 2018 - 17 :37:30) r- MAC_ADDR not setting Factory Address:0x2000000, Size:0x800000! Factory Read Only Address:0x1800000, Size:0x400000! anel_filename NULL>>>>>>>>>> ==== James panel000 env_panel_set_default line:293 file=env_panel.c panel_select =Panel: benq22_panel_portswap_VESA.h logbuf fifo[0] [buffer=1ca0e000], [size=10000] logbuf fifo[1] [buffer=1ca1e000], [size=2000] logbuf fifo[2] [buffer=1ca20000], [size=10000] logbuf fifo[3] [buffer=1ca30000], [size=10000] logbuf fifo[4] [buffer=1ca40000], [size=10000] logbuf fifo[5] [buffer=1ca50000], [size=20000] logbuf fifo[6] [buffer=1ca70000], [size=10000] SCPU2: BISR hold remap SCPU2: BISR ok 0 In: serial Out: serial Err: serial Net: r8168: REALTEK RTL8168 @0x18016000 panel_init_1st 0529_1022 Hit Esc or Tab key to enter console mode or rescue linux: 0 (Re)start USB... USB0: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac0 ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_on ----------- ----------- snps_reset_release ----------- ----------- internal_ldo_on ----------- [ehci], info, #@# usb2_phy_setting(308) +++ for usbphy setting 20170420 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 Disp HTotal=2199, Htotal 4x alignment=2199 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x18 get 0x18 den_h_start=140, den_h_end=2060 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [uzu] dvtotal(b8028504 = 464) [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x4d get 0x4d [uzu] dhtotal(b8028508 = 8970897) [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [uzu] dh den start(b8028518 = 8c080c) [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xcd get 0xcd [uzu] dv den start(b802851c = 100448) [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [uzu] uzudtg control (b8028500 = 80000051) [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x63 get 0x63 [memc] dvtotal(b8028604 = 464) [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [memc] dhtotal(b8028608 = 8970897) [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [memc] dh den start(b802861c = 8c080c) [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x53 get 0x53 [memc] dv den start(b8028618 = 100448) [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x53 get 0x53 [memc] uzudtg control (b8028100 = 50000) [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b ###### SFG_SFG_CTRL_0_reg : 1 ######## [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b ###### 1. 0xB802D9B8 : 1 ######## [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c ##### drvif_clock_set_dclk : 148900000 ########### [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x6c get 0x6c After Mapping (ulFreq:595600000) (div:4)====== [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 dclk_Temp:661777 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x81 get 0x81 nMCode:66, f_code:363 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb Panel: ulFreq:595600000, nDPLL:0, Mcode:66, Ncode:3, offset:0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 #### 0xb8000208[7e] [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 #### [drvif_clock_set_dtg_uzu_div] [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb #### 0xb8000208[400007e] [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x23 get 0x23 #### [drvif_clock_set_dtg_memc_div] [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x27 get 0x27 === Panel Type : 0 === [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b ====284x panel_lvds_tx ===== [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b === Panel Index : 0 === [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_phy_setting(310) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found USB1: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac1 [ehci], info, #@# usb2_ex_phy_setting(315) +++ for usbphy setting 20170420 ----------- _usb2_ex_load_phy_setting ----------- [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x53 get 0x58 <---- not matched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xa8 get 0x27 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x11 get 0x70 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0xe3 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xb8 get 0x12 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x15 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x81 get 0xf <---- not m atched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_ex_phy_setting(317) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 1 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found 1: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 2: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 3: Vendor specific, USB Revision 2.0 - Realtek 802.11n NIC 00C30E02623A - Class: (from Interface) Vendor specific - PacketSize: 64 Configurations: 1 - Vendor: 0x0bda Product 0x0179 Version 0.0 Configuration: 1 - Interfaces: 1 Bus Powered Remote Wakeup 500mA Interface: 0 - Alternate Setting 0, Endpoints: 3 - Class Vendor specific - Endpoint 1 In Bulk MaxPacket 512 - Endpoint 2 Out Bulk MaxPacket 512 - Endpoint 3 Out Bulk MaxPacket 512 ** Invalid boot device ** [WARN] check_usb_into_factory_mode:read install.img failed. (No such file) stopping USB.. ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_off ----------- ====== boot_ac_on=1 ====== (Re)start USB... USB0: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac0 ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_on ----------- ----------- snps_reset_release ----------- ----------- internal_ldo_on ----------- [ehci], info, #@# usb2_phy_setting(308) +++ for usbphy setting 20170420 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x53 get 0x53 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x53 get 0x53 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_phy_setting(310) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found USB1: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac1 [ehci], info, #@# usb2_ex_phy_setting(315) +++ for usbphy setting 20170420 ----------- _usb2_ex_load_phy_setting ----------- [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x53 get 0x58 <---- not matched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xa8 get 0x27 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x11 get 0x70 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0xe3 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xb8 get 0x12 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x15 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x81 get 0xf <---- not m atched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_ex_phy_setting(317) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 1 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found 1: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 2: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 3: Vendor specific, USB Revision 2.0 - Realtek 802.11n NIC 00C30E02623A - Class: (from Interface) Vendor specific - PacketSize: 64 Configurations: 1 - Vendor: 0x0bda Product 0x0179 Version 0.0 Configuration: 1 - Interfaces: 1 Bus Powered Remote Wakeup 500mA Interface: 0 - Alternate Setting 0, Endpoints: 3 - Class Vendor specific - Endpoint 1 In Bulk MaxPacket 512 - Endpoint 2 Out Bulk MaxPacket 512 - Endpoint 3 Out Bulk MaxPacket 512 ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_off ----------- (Re)start USB... USB0: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac0 ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_on ----------- ----------- snps_reset_release ----------- ----------- internal_ldo_on ----------- [ehci], info, #@# usb2_phy_setting(308) +++ for usbphy setting 20170420 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x53 get 0x53 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x53 get 0x53 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0xdb get 0xdb [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe0 set 0xa8 get 0xa8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe1 set 0x11 get 0x11 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe2 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe3 set 0xb8 get 0xb8 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe4 set 0x15 get 0x15 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xe5 set 0x81 get 0x81 [ehci], dbg, set_usb2_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_phy, port 2 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_phy_setting(310) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 0 for devices... 1 USB Device(s) found USB1: ----------- ehci_hcd_init ----------- #@# ehci_hcd_init(404) ehci mac1 [ehci], info, #@# usb2_ex_phy_setting(315) +++ for usbphy setting 20170420 ----------- _usb2_ex_load_phy_setting ----------- [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x18 get 0x18 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x4d get 0x4d [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xcd get 0xcd [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x63 get 0x63 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x53 get 0x58 <---- not matched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x6c get 0x6c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x81 get 0x81 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x23 get 0x23 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0x27 get 0x27 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x7c get 0x7c [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0x41 get 0x41 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf0 set 0xfc get 0xfc [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf1 set 0x88 get 0x88 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf3 set 0x31 get 0x31 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf5 set 0x15 get 0x15 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf6 set 0x1 get 0x1 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf7 set 0xa get 0xa [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xbb get 0xbb [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x70 get 0x70 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0x12 get 0x12 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x0 get 0x0 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0xf get 0xf [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe6 set 0x58 get 0x58 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xe7 set 0xe3 get 0xe3 [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0xdb get 0xdb [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe0 set 0xa8 get 0x27 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe1 set 0x11 get 0x70 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe2 set 0xe3 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe3 set 0xb8 get 0x12 <---- not matched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe4 set 0x15 get 0x0 <---- not m atched [ehci], warn, set_usb2_ex_phy, port 1 phy_reg 0xe5 set 0x81 get 0xf <---- not m atched [ehci], dbg, set_usb2_ex_phy, port 1 phy_reg 0xf4 set 0x9b get 0x9b [ehci], info, #@# usb2_ex_phy_setting(317) --- ----------- ehci_usb_mac_init ----------- USB EHCI 1.00 scanning bus 1 for devices... 2 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found 1: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 2: Hub, USB Revision 2.0 - u-boot EHCI Host Controller - Class: Hub - PacketSize: 64 Configurations: 1 - Vendor: 0x0000 Product 0x0000 Version 1.0 Configuration: 1 - Interfaces: 1 Self Powered 0mA Interface: 0 - Alternate Setting 0, Endpoints: 1 - Class Hub - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms 3: Vendor specific, USB Revision 2.0 - Realtek 802.11n NIC 00C30E02623A - Class: (from Interface) Vendor specific - PacketSize: 64 Configurations: 1 - Vendor: 0x0bda Product 0x0179 Version 0.0 Configuration: 1 - Interfaces: 1 Bus Powered Remote Wakeup 500mA Interface: 0 - Alternate Setting 0, Endpoints: 3 - Class Vendor specific - Endpoint 1 In Bulk MaxPacket 512 - Endpoint 2 Out Bulk MaxPacket 512 - Endpoint 3 Out Bulk MaxPacket 512 ** Invalid boot device ** ac_on_update_mac_address mac.bin exist! No need update mac again. ac_on_update_CI_key:2726 Error: reading boot sector first_CiKey: reading cikey.used Error: reading boot sector cikey_file_name=CiPlusKey/ reading CiPlusKey/ Error: reading boot sector file_fat_read failed!!!!! ac_on_update_hdcp_key:2606 Error: reading boot sector first_HDCP: reading hdcpwrited.used Error: reading boot sector hdcp_file_name=HDCP/ reading HDCP/ Error: reading boot sector read HDCP file fail ac_on_update_hdcp_key22:2666 Error: reading boot sector first_HDCP: reading hdcp2writed.used Error: reading boot sector hdcp_file_name=HDCP2/ reading HDCP2/ Error: reading boot sector read HDCP2 file fail stopping USB.. ----------- usb2_clk_setting_off ----------- ----------- usb2_clk_setting_off ----------- Start Boot Setup ... s_cmdline(0) = "" s_cmdline(0) = "" s_cmdline(0) = "" FW Table to 0x0e900000, size=0x00000800 (0x0e900800) FW Table fr 0x03800000, fw count: 50 [OK] fw_entry[0] offset = 0x8000 length = 0x170e100 (paddings = 0x1c00000) act_s ize = 0 part_num = 0 [OK] fw_entry[1] offset = 0x1c08000 length = 0x21bf30 (paddings = 0x500000) act_ size = 0 part_num = 0 [OK] fw_entry[2] offset = 0x2108000 length = 0x34feb0 (paddings = 0x600000) act_ size = 0 part_num = 0 [OK] fw_entry[3] offset = 0x2708000 length = 0x58678 (paddings = 0xc00000) act_s ize = 0 part_num = 0 [OK] fw_entry[4] offset = 0x3308000 length = 0x2a3000 (paddings = 0x2a3000) act_ size = 0 part_num = 0 Normal boot fw follow... Linux Kernel: FW Image to 0x00108000, size=0x0170e100 (0x01816100) FW Image fr 0x03808000 (non-lzma) Audio FW 1: FW Image to 0xdeaddead, size=0x0021bf30 (0xdecf9ddd) FW Image fr 0x05408000 (non-lzma) Enter standby, skip this entry Video FW 1: FW Image to 0xdeaddead, size=0x0034feb0 (0xdee2dd5d) FW Image fr 0x05908000 (non-lzma) Enter standby, skip this entry TEE FW target_addr = 0x16008000 KCPU FW: (skip) show raw video raw file ddr 0x84f00000 len 0x302a00 FW Image to 0x84f00000, size=0x002a3000 (0x851a3000) FW Image fr 0x06b08000 (non-lzma) Enter standby, skip this entry ====================================================== the first 32-byte encrypted data(base=0x0b000000) 000 : c0 c2 58 bb d8 b1 1a cf fc 6d 23 4f 02 d4 d7 b7 010 : b4 80 c4 9a d6 77 24 4c 3f 92 79 0e 1f 45 84 9d ====================================================== the first 32-byte decrypted data(base=0x00108000) 000 : b0 4f 10 ee 01 5c 04 e2 01 0c 55 e3 04 00 00 0a 010 : 03 40 04 e2 00 00 54 e3 16 00 00 0a 01 00 54 e3 sw sha256 ret 0 ==== IO_Set(PIN_AMP_MUTE, 0);